1. Field of the Invention
The present invention relates to the control of data to be written to memory components. More particularly, the present invention relates to a structure and method for implementing bit and byte enable signals and logic during write operations to memory components.
2. Art Background
FIG. 1 shows some of the common features of modern solid-state memory components. The memory components contain a two dimensional array of storage cells. These storage cells may be static (i.e. there is a bistable latch) or dynamic (i.e. there is a single capacitor holding a charge). A row of storage cells is read when a row address is applied to the row decoder and the appropriate read control signals are asserted. This entire row is held in a row of column amplifiers (sense amplifiers) which are typically static in nature. Any subset of this sensed row may be accessed via column addresses and control signals.
A write operation requires additional control. It is important to be able to write to a subset of a row. This is typically done as a two step process (although in a static memory component it may be done as a single step). The information to be written is placed on the write data signal lines. The write enable signal is asserted for only those bits of a row which have been selected by the column select circuitry and which are to be modified. Write enable signals are not asserted for the remaining bits. The Read/Write Column signal is then asserted, permitting those sense amplifiers of the row with the write enable signal asserted to be modified with the write data received across the write data signal lines. Subsequently, using the write row signals, the entire row may be rewritten from the column amplifiers back to the RAM array, with the subset of the storage cells modified according to the modified bits in the column amplifiers.
This technique works because the sense amplifier retains previous data written to the sense amplifier if the two write drivers driven by the write enable are allowed to float (write enable is not asserted). Although internally there is typically a write enable signal for each bit of write data, these signals are not available externally; therefore, most memory components are incapable of modifying any pattern of bits within a row.
FIG. 3 shows an example of a prior art memory component with byte enable controls for write masking. FIG. 3, and succeeding figures, use the notation set forth in FIG. 2.
In the prior art memory components, the value of m is typically one or two. The memory array 110 and the data receiver 115 typically transact the same quantum of information (m*b bits). There are typically "m" write enable signals for masking the individual bytes of write data within this transaction quantum, where m represents the number of bytes of data communicated by the memory component. The masking is controlled by the byte enable controls 120. The copy block duplicates the bit on the one input wire onto the "b" output wires.
FIGS. 4 and 5 illustrate another example of prior art in which the memory component includes a bit enable register (BitMask) 180 and write data register (WriteReg) 185. In addition to the byte enable control lines shown in the previous example of FIG. 3, two loadable internal registers, BitMask 180 and WriteReg 185 are connected to the receiver 190 for the data lines 195. Two multiplexers 200, 205 are provided for selecting the receiver 190 contents (the receivers typically have register or latch storage elements) or the contents of the two loadable registers 180, 185 for input to the write enable 210 and write data 215 input pins of the memory array 220.
As set forth in FIG. 4, this configuration permits several modes of operation. The first mode provides the functionality of the previous example set forth in FIG. 3. The second and sixth modes provide additional functionality.
FIG. 6 illustrates a simplified timing diagram for the second mode. It should be noted that the signals for the row and column portions of the address are multiplexed together. In a typical operation, a row address is received and latched by the memory component, and followed by multiple column addresses in subsequent clock cycles to access the sensed row. Referring to FIGS. 5 and 6, when the row address Rowa! is received on the address lines 225, the BitMaska! value is also received on the data lines 195. The BitMaska! value is latched by the bit mask register 180, and is used to perform bit masking on incoming data until a new value is received to overwrite it.
When each column address Cola,i! is received on the address lines 225, the WDataa,i! value is also received on the data lines 195. This value is held in the receiver 190, and is used to drive the write data inputs 215 of the memory array 220. This is repeated for "n" different values of WData, using the same value of BitMask stored in the bit mask register 180. When the next row address Rowb! is received on the Address lines 225, a new BitMaskb! value is also received on the data lines 195. A second series of column write operations is then performed with the new bit mask value.
FIG. 7 shows a simplified timing diagram for Mode Six. Referring to FIGS. 5 and 7, when the row address Rowa! is received on the address lines 225, the WDataa! value is also received on the data lines 195. This value is latched by the WriteReg register 185, and is used until a new WData value is received and overwrites the value in the register 185. Thus, when each column address Cola,i! is received on the address lines 225, the BitMaska,i! value is also received on the data lines 195. This value is held in the receiver 190, and subsequently drives the Write enable inputs 210 of the Memory Array 220. This is repeated for "n" different values of the bit mask, using the same value stored in the WriteReg 185.
When the next row address Rowb! is received on the address lines 225, a new WDatab! value is also received on the data lines 195. A second series of column write operations is then performed using the new WDatab! value.